Fishing – trapping – and vermin destroying
Patent
1994-05-19
1996-03-05
Fourson, George
Fishing, trapping, and vermin destroying
437235, 437236, 437195, 437 40, H01L 2144, H01L 2148
Patent
active
054967716
ABSTRACT:
Fabrication methods and resultant semiconductor structures wherein stack structures are selectively insulated from an enveloping layer of local interconnect material. The fabrication methods involve forming an overpass insulator(s) simultaneously with the underlying gate. Specifically, a layer of non-erodible insulating material is deposited over a layer of conductive material roughly in the area to comprise the stack structure. A simultaneous etch is then performed, and the resultant insulator portion is self-aligned to the underlying conductive material. The insulator portion insulates the stack from a subsequently deposited and planarized layer of local interconnect. Further processing options include decoupling silicide formation on selected stack structures, and various planarization and etching approaches for different available technologies. Specific details of the fabrication methods and resultant structures are set forth.
REFERENCES:
patent: 4505030 (1985-03-01), Jeuch
patent: 4789648 (1988-12-01), Chow et al.
patent: 4808552 (1989-02-01), Anderson
patent: 4933743 (1990-06-01), Thomas et al.
patent: 4944836 (1990-07-01), Beyer et al.
Cronin John E.
Kaanta Carter W.
Mann Randy W.
Meulemans Darrell
Starkey Gordon S.
Everhart C.
Fourson George
International Business Machines - Corporation
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