Semiconductor memory with delay means to reduce peak currents

Details Semiconductor memory with delay means to reduce peak currents Semiconductor memory with delay means to reduce peak currents

1982-05-19

1985-12-03

Hecker, Stuart N.

Static information storage and retrieval

Read/write circuit

Signals

365203, 365227, 365205, G11C 1140, G11C 700

Patent

active

045569614

ABSTRACT:
A semiconductor device comprises a plurality of data supply circuits, output circuits for producing a plurality of data delivered from the data supply circuit and delay circuit for transferring respective data from each data supply circuit to a different output circuit with a different delay time. Each data supply circuit includes a plurality of row lines, a row decoder for selecting the row line in response to an address signal, a plurality of memory cell arrays including memory cells selectively driven by the row line and storing data, a plurality of column lines to receive data read out from the memory cell array, and a column decoder for selecting said column lines. The delay circuit prevents a plurality of data from being simultaneously outputted.

REFERENCES:
patent: 3688264 (1972-08-01), Dingwall
patent: 3706078 (1972-12-01), Hilberg
patent: 3866061 (1975-02-01), Wen et al.
patent: 4045785 (1977-08-01), Kirkpatrick, Jr.
patent: 4204277 (1980-05-01), Kinoshita
patent: 4222112 (1980-09-01), Clemons et al.
patent: 4344156 (1982-08-01), Eaton, Jr. et al.
patent: 4354256 (1982-10-01), Miyasaka
patent: 4417328 (1983-11-01), Ochii
General Instrument's New 8,192-Bit Earom Relies on Metal-Nitride-Oxide Technology . . . Electronics 40 (Sep. 16, 1976).

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