Logic gate with controllable hysteresis and high frequency volta

Electronic digital logic circuitry – Signal sensitivity or transmission integrity – Input noise margin enhancement

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326 83, 327206, H03K 1716, H03K 19094

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active

055943616

ABSTRACT:
A hysteresis circuit comprises a first logic section, a second logic section cascaded with the first logic section, and circuitry for controlling hysteresis threshold voltages of the hysteresis circuit. The hysteresis controlling circuitry conducts current from a source of a first supply voltage to the output lead of the first logic section during a low-to-high transition of an input voltage on an input terminal of the hysteresis circuit. The hysteresis controlling circuitry conducts current from the output lead of the first logic section to a source of a second supply voltage during a high-to-low transition of the input voltage on the input terminal of the hysteresis circuit. A clock generator integrated circuit chip employing the hysteresis circuit in a voltage controlled oscillator can generate squarewave signals of 150 MHz onto a plurality of output terminals when powered from approximately 3.3 volts throughout a 0 to 70 degree Celsius temperature range, a clock skew of less than 0.5 nanosecond existing between the squarewave signals on the output terminals.

REFERENCES:
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patent: 4571504 (1986-02-01), Iwamoto et al.
patent: 4603264 (1986-07-01), Nakano
patent: 5122680 (1992-06-01), Stakely et al.
patent: 5334883 (1994-08-01), Rosenthal
patent: 5386153 (1995-01-01), Voss et al.
patent: 5461331 (1995-10-01), Schorn

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