Synchronous semiconductor memory device having a mode requiring

Details Synchronous semiconductor memory device having a mode requiring Synchronous semiconductor memory device having a mode requiring

1995-09-08

1997-05-13

Nelms, David C.

Static information storage and retrieval

Read/write circuit

Signals

365222, 365233, G11C 800

Patent

active

056298978

ABSTRACT:
A refresh control circuit of a DLL circuit responds to an auto refresh detection signal AR and a self refresh detection signal SR to inhibit input of clock signals ECLK and RCLK to a phase comparator and to a voltage control delay circuit. The DLL circuit can be stopped in a mode where an internal clock signal is not required to reduce power consumption.

REFERENCES:
patent: 5444667 (1995-08-01), Obara
patent: 5469386 (1995-11-01), Obara
patent: 5477491 (1995-12-01), Shirai
patent: 5495452 (1996-02-01), Cha
Natsuki Kushiymam et al, IEEE Journal of Solid-State Circuits, vol. 28, No. 4, "A 500 Megabyte/s Data-Rate 4.5M DRAM", Apr. 1993, pp. 490-497.

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