Semiconductor memory device having thin film transistor and meth

Details Semiconductor memory device having thin film transistor and meth Semiconductor memory device having thin film transistor and meth

1994-01-04

1997-01-14

Meier, Stephen

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

257377, H01L 2976, H01L 2994, H01L 31062, H01L 31113

Patent

active

055942679

ABSTRACT:
A semiconductor memory device includes a semiconductor substrate, and a memory cell formed on the semiconductor substrate and including two transfer transistors, two driver transistors and two thin film transistor loads. The thin film transistor load includes a first gate electrode, a first insulator layer formed on the first gate electrode, a semiconductor layer formed on the first insulator layer, a second insulator layer formed on the semiconductor layer, and a shield electrode formed on the second insulator layer. This shield electrode shields the thin film transistor.

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patent: 4853894 (1989-08-01), Yamanaka et al.
patent: 4931410 (1990-06-01), Tokunaga et al.
Sze et al, Semiconductor Devices, Physics& Tech., pp. 341--362, 1985.
Chen et al, `A New Device for Interconnect Scheme . . . `, IEPM-84, pp. 118-120.
Yamanaka et al., "A 25 .mu.m.sup.2 New Poly-Si PMOS Load (PPL) SRAM Cell Having Excellent Soft Error Immunity", International Electron Devices Meeting, Dec. 1988, San Francisco, CA, pp. 48-51.
Ando et al., "A 0.1-.mu.A Standby Current, Ground-Bounce-Immune 1-Mbit CMOS SRAM", IEEE Journal of Solid-State Circuits, vol. 24, No. 6, Dec. 1989, New York, NY, pp. 1708-1713.
Ishibashi et al., "An .alpha.-Immune, 2-V Supply Voltage SRAM Using a Polysilicon PMOS Load Cell", IEEE Journal of Solid-State Circuits, vol. 25, No. 1, Feb. 1990, New York, NY, pp. 55-60.
Adan et al., "A Half-Micron SRAM Cell Using a Double-Gated Self-Aligned Polysilicon PMOS Thin Film Transistor (TFT) Load", Symposium on VLSI Technology, Jun. 1990, Honolulu, Japan, pp. 19-20.

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