System for simultaneously writing back cached data via first bus

Details System for simultaneously writing back cached data via first bus System for simultaneously writing back cached data via first bus

1997-02-26

1999-06-29

Lee, Thomas C.

Electrical computers and digital processing systems: memory

Storage accessing and control

Hierarchical memories

395722, 395861, 711118, 711138, 711143, 711146, G06F 1316

Patent

active

059180692

ABSTRACT:
A bus bridge mutually connects a CPU bus to which a CPU and a corresponding cache memory having a write-back scheme are coupled, an I/O bus to which a bus master is coupled, and a main memory which is commonly accessed through the CPU bus or I/O bus. In response to an access request from the bus master to the main memory, a cache snooping section snoops a cache memory to see whether an address in the access request satisfies a cache hit or miss, and data corresponding to the address is dirty or clear. In response to a snooping result by the cache snooping section indicating that the cache hit has occurred and the data is dirty, a write-back control section writes back the data from the cache memory in the main memory. In the case where the access request indicates a read request, a data bypass section directly transfers the data from the cache memory onto the I/O bus while the write-back control section performs writing back. With this processing, data read processing from the main memory need not wait for completion of write-back processing with respect to the main memory. Therefore, even if a cache write-back operation is performed in response to a main memory access request from the bus master, the main memory access operation can be performed at a high speed.

REFERENCES:
patent: 4344713 (1982-08-01), Cullen
patent: 5111386 (1992-05-01), Fujishima et al.
patent: 5634112 (1997-05-01), Thome et al.
patent: 5729546 (1998-03-01), Gupta et al.

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