Electrical computers and digital processing systems: memory – Storage accessing and control – Control technique
Patent
1996-07-01
1999-04-06
Cabeca, John W.
Electrical computers and digital processing systems: memory
Storage accessing and control
Control technique
711144, 395860, G06F 1200
Patent
active
058931651
ABSTRACT:
A data processor supports the use of multiple memory models by computer programs. At a device external to a data processor, such as a memory controller, memory transactions requests are received from the data processor. Each memory transaction request has associated therewith a memory model selected from a predefined plurality of memory models. In a preferred embodiment, the predefined memory models supported are SSO (strong sequential order), TSO (total store order), PSO (partial store order) and RMO (relaxed memory order). Data representing pending memory transactions are stored in one or more pending transaction buffers and a pending transaction status array. The pending transaction status data includes memory transaction order data that indicates which of the pending memory transactions can be performed before other ones of the pending memory transactions. More particularly, logic in the memory controller determines, based on the memory model associated with a most recently received memory transaction request and the memory model associated with at least one other pending memory transaction, whether or not the memory transaction associated with the most recently received memory transaction request can be performed before the other pending memory transaction, and then stores data representing this ordering determination in a transaction scoreboard. The memory controller performs the pending memory transactions in an order consistent with the memory transaction order data. As a result, a subset of the pending memory transactions are performed in a different order than they were received from the data processor.
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Cabeca John W.
Langjahr David
Sun Microsystems Inc.
Williams Gary S.
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