Memory architecture and devices, systems and methods utilizing t

Details Memory architecture and devices, systems and methods utilizing t Memory architecture and devices, systems and methods utilizing t

1994-09-12

1995-12-05

Nelms, David C.

Static information storage and retrieval

Read/write circuit

With shift register

36523003, 36523009, 36523005, 3652385, 365240, 365219, G11C 700

Patent

active

054735661

ABSTRACT:
A memory 200 is provided which includes a plurality of self-contained memory units 201 for storing data. A plurality of shift registers 211 are provided, each including a first parallel port coupled to a data port of a corresponding one of the self-contained memory units 201. Interconnection circuitry 212 is coupled to a parallel data port of each of the shift registers. Control circuitry 208, 213 is provided which is operable to control the exchange of data between a selected one of the memory units and the interconnection circuitry 212 via the shift register 211 coupled to the selected memory unit 201.

REFERENCES:
patent: 4987559 (1991-01-01), Miyauchi et al.
patent: 5161221 (1992-11-01), Van Abstrand
patent: 5200925 (1993-03-01), Morooka
patent: 5270973 (1993-12-01), Guillemand et al.
patent: 5377154 (1994-10-01), Takasugi

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