Semiconductor memory cell for holding data with small power cons

Details Semiconductor memory cell for holding data with small power cons Semiconductor memory cell for holding data with small power cons

1991-11-22

1994-10-25

Jackson, Jerome

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

257297, 257301, 257302, 257306, H01L 2978

Patent

active

053592158

ABSTRACT:
A DRAM includes an N-type well formed on a main surface of a P-type semiconductor substrate, an N-type impurity region formed on the main surface of the P-type semiconductor substrate, a P-type impurity region formed in the N-type well to be a storage node of a memory capacitor, and a polycrystalline silicon layer for connecting the P-type impurity region and the N-type impurity region. The N-type impurity layer, the P-type impurity layer, and the polycrystalline silicon layer constitute the storage node of the memory capacitor, and electrons of minority carriers flowing from the substrate to the N-type impurity layer are recombined with holes flowing from the N-type well to the P-type impurity layer.

REFERENCES:
patent: 4151610 (1979-04-01), Suzuki et al.
patent: 4156939 (1979-05-01), Takemae et al.
patent: 4392210 (1983-07-01), Chan
patent: 4927779 (1990-05-01), Dhong et al.
patent: 4937645 (1990-06-01), Ootsuka et al.
patent: 5006909 (1991-04-01), Kosa

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