Exponentiation remainder operation circuit

Details Exponentiation remainder operation circuit Exponentiation remainder operation circuit

1993-12-07

1995-12-26

Envall, Jr., Roy N.

Boots, shoes, and leggings

364749, G06F 738

Patent

active

054793653

ABSTRACT:
An exponentiation remainder operation circuit includes a first exponentiation remainder operator for performing an exponentiation remainder operation for a n/2 bit length parameter, in which n is an even number, a second exponentiation remainder operator, a first adder/subtractor for performing addition and subtraction for a n/2 bit length parameter, a second adder/subtractor, and a central processing unit (CPU) for performing an exponentiation remainder operation for a n-bit length parameter by controlling the exponentiation remainder operation of the first exponentiation remainder operator for the upper n/2 bits of the n-bit length parameter, the exponentiation remainder operation of the second exponentiation remainder operator for the lower n/2 bits of the n-bit length parameter, and addition and subtraction of the results of operations of the first and second exponentiation remainder operators by the first and second adders/subtractors.

REFERENCES:
patent: 4870681 (1989-09-01), Seldack
patent: 5046094 (1991-09-01), Kawamura et al.
patent: 5289397 (1994-02-01), Clark et al.

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