Mybrid charge-transfer-device filter structure

Details Mybrid charge-transfer-device filter structure Mybrid charge-transfer-device filter structure

1985-08-26

1989-02-28

Harkcom, Gary V.

Boots, shoes, and leggings

36472403, G06F 1531

Patent

active

048092096

ABSTRACT:
A signal processor suitable for use as a discrete-time or sampled-data analog filter can be implemented by using only a few of the coefficient multipliers of a typical analog finite-impulse-response (FIR) filter, and expressing each coefficient multiplier as a multibit digital word. Each bit of the multibit word is formulated as a tap weight coupled to a delay element of an input-delay line. Factor elements are coupled to the outputs of the bit-tap-weights to multiply the outputs of those bit-tap-weights by factors representative of the significance of the bit represented by that weight. Bit-tap weight outputs from tabs that were lens delayed on the input line are delayed upon output so the outputs of all the bit-tap weights associated with a single multibit word are combined together to form a single output. The output signal is interpolated in an interpolator to recover the information lost by omitting some of the coefficient multipliers.

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