Semiconductor device having an electrode and a method of manufac

Details Semiconductor device having an electrode and a method of manufac Semiconductor device having an electrode and a method of manufac

1988-05-05

1989-02-28

James, Andrew J.

357 67, 357 54, H01L 2354, H01L 2314

Patent

active

048090557

ABSTRACT:
An SiO.sub.2 insulating layer is formed on an Si substrate, and an Si.sub.3 N.sub.4 insulating layer is formed on the SiO.sub.2 layer. A notch is formed in the Si.sub.3 N.sub.4 layer using a resist film as a mask. The SiO.sub.2 layer is etched using the Si.sub.3 N.sub.4 layer as a mask, thereby forming an opening larger than the notch cut in the SiO.sub.2 layer. As a result, the Si.sub.3 N.sub.4 layer extends over the opening in an overhanging manner. When As.sup.+ ions are implanted in the periphery of the notch of the Si.sub.3 N.sub.4 layer, the ion-implanted portion of the Si.sub.3 N.sub.4 layer is arcuated toward the base region. When a metal such as Ti is deposited on the arcuated portion, the metal is also deposited on the arcuated portion and the portion of the emitter region matching with the notch, thereby forming an emitter electrode portion.

REFERENCES:
patent: 3763408 (1973-10-01), Kano et al.
patent: 4210689 (1980-07-01), Komatsu
patent: 4516147 (1985-05-01), Komatsu et al.
patent: 4532004 (1985-07-01), Akiyama et al.
"Method of Minimizing Al-Si Alloying in Semiconductor Devices"-IBM Technical Disclosure Bulletin-vol. 29, No. 10, Mar. 1987, pp. 4626-4627.
"Method of Contacting Shallow Emitters"-Barson-IBM Technical Disclosure Bulletin-vol. 23, No. 9, Feb-1981, pp. 4135-4136.

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