Method for forming a field-effect transistor having difference i

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – On insulating substrate or layer

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438479, 438526, 438286, H01L 2100, H01L 2184

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active

058917578

ABSTRACT:
A field-effect transistor has a source region, a drain region, a gate electrode, and a low resistivity layer. The source and drain regions are of a first conductivity type and formed as surface regions of a semiconductor layer formed on one of an insulating substrate and a semi-insulating substrate. The gate electrode is formed on a channel region between the source region and the drain region. The low resistivity layer serving as a shield layer is disposed underneath and spaced apart from the source, drain and channel regions, and overlaps the source region with an overlap area being larger than an overlap area between the low resistivity layer and the drain region. The arrangement enables the prevention of noise margin reduction and erroneous operation.

REFERENCES:
patent: 4864377 (1989-09-01), Widdershoven
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patent: 5488243 (1996-01-01), Tsuruta et al.
patent: 5514608 (1996-05-01), Williams et al.
patent: 5548150 (1996-08-01), Omura et al
"Suppression of Drain Conductance Transients, Drain Current Oscillations, and Low-Frequency Generation-Recombinatin Noise in GaAs FET's Using Buried Channels" Canfield et al: IEEE Transactions on Electron Devices, vol. ED-33; No. 7; Jul. 1986; pp. 925-928.
"Effects of Neutral Buried p-Layer on High-Frequency Performance of GaAs MESFET's " Onodera et al IEEE Transactions on Electron Devices, vol 38; No. 3; Mar. 1991; pp. 429-436.
"Buried-Channel GaAs MESFET's with Frequency-Independent Output Conductance" Canfield et al IEEE Electron Device LEtters, vol. EDL-8; No. 3; Mar. 1987 pp. 88-89.

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