MOS electrostatic discharge protection device and structure

Details MOS electrostatic discharge protection device and structure MOS electrostatic discharge protection device and structure

1993-09-23

1995-12-26

Jackson, Jerome

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

257360, 257363, 361 91, 361111, H01L 2906, H01L 2978

Patent

active

054790395

ABSTRACT:
A PMOS transistor is coupled directly to both V.sub.CC and V.sub.SS, for use in an electrostatic discharge (ESD) protection device, thereby protecting the I/O pad(s) of an integrated circuit. The direct coupling of the PMOS transistor to both voltage levels, V.sub.CC and V.sub.SS, greatly reduces the overall ESD hazard, i.e, to all four ESD conditions: 1) positive against V.sub.SS, 2) negative against V.sub.SS, 3) positive against V.sub.CC, and 4) negative against V.sub.CC, the most critical of these tests being the positive against V.sub.SS and positive against V.sub.CC.

REFERENCES:
patent: 3967295 (1975-06-01), Stewart
patent: 4786956 (1988-11-01), Puar
patent: 4821096 (1989-04-01), Maloney
Sze, "Semiconductor Devices Physics and Technology," 1985, pp. 202 and 212.

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