Method of making a trench DRAM cell with dynamic gain

Details Method of making a trench DRAM cell with dynamic gain Method of making a trench DRAM cell with dynamic gain

1990-08-16

1991-11-19

Hearn, Brian E.

Fishing, trapping, and vermin destroying

437 37, 437 47, 437 51, 437 60, 437228, 437233, 437235, 437919, H01L 2170

Patent

active

050666070

ABSTRACT:
A two transistor gain-type DRAM cell (8) is formed in a trench (30) to optimize wafer area requirements. Formed on a heavily doped semiconductor substrate (20) are alternate layers of P-type and N-type semiconductor material defining the elements of a vertical pass transistor (12) and gain transistor (24). A trench is formed through the alternate semiconductor layers into the substrate (20), and filled with two regions of a semiconductor material defining a storage node (18) and, insulated therefrom, a word line (16). The gain transistor (24) is fabricated having a response time faster than that of the pass transistor (12) so that, during read operations, the gain transistor (24) changes the precharged voltage of the read bit line (26), depending upon the charge stored in the capacitor storage node (18).

REFERENCES:
patent: 4623989 (1988-11-01), Blake
patent: 4716548 (1987-12-01), Mochizuki
patent: 4751557 (1988-06-01), Sunami et al.
patent: 4864374 (1989-09-01), Banerjee
Nicky C. C. Lu, "Advanced Cell Structures for Dynamic RAMs", IEEE Circuits and Devices Magazine, Jan. 1989, pp. 27-35.

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