Process for fabricating a stashed capacitor in a semiconductor d

Details Process for fabricating a stashed capacitor in a semiconductor d Process for fabricating a stashed capacitor in a semiconductor d

1994-12-28

1995-12-26

Chaudhuri, Olik

Fishing, trapping, and vermin destroying

437 60, 437919, H01L 2170, H01L 2700

Patent

active

054787696

ABSTRACT:
There is a process for fabricating a capacitor of a semiconductor device, distinguished by characteristic steps consisting broadly of laminating an impurity-doped amorphous layer and a pure amorphous layer, alternately and in at least two folds, annealing the multiplicate amorphous layer to polycrystallize it and to diffuse the impurities, utilizing an oxide pattern and a nitride spacer formed at the sidewall of the oxide pattern to form a cylindrical storage electrode consisting of the resulting polysilicon layers, and taking advantage of etch selectivity difference between the doped and undoped polysilicon layers to form grooves in the cylindrical storage electrode. Such storage electrode has a larger surface area than conventional storage electrodes do, in the same space occupied. Therefore, the fabrication process brings about effects that the high integration of semiconductor device can be accomplished and the reliability of device operation can be improved.

REFERENCES:
patent: 5053351 (1991-10-01), Fazan et al.
patent: 5281549 (1994-01-01), Fazan et al.

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