Local interconnect process for integrated circuits

Details Local interconnect process for integrated circuits Local interconnect process for integrated circuits

1992-11-30

1995-12-05

Quach, T. N.

Fishing, trapping, and vermin destroying

437192, 437200, H01L 21283

Patent

active

RE0351113

ABSTRACT:
A silicide layer, to improve conductivity, is formed over a first layer of polycrystalline silicon, followed by a second layer of polycrystalline silicon. This structure is then patterned to form gate regions over active areas. A layer of metal silicide is formed over the entire surface of the chip, and patterned to form local interconnect. Etching of the second metal silicide layer is stopped by the second polycrystalline silicon layer, thereby protecting the rust metal silicide layer from damage.

REFERENCES:
patent: 4470189 (1984-09-01), Roberts et al.
patent: 4640738 (1988-02-01), Fredericks et al.
patent: 4690730 (1987-09-01), Tang et al.
patent: 4708904 (1987-11-01), Shimizu et al.
patent: 4740484 (1988-04-01), Norstrom et al.
patent: 4774204 (1988-09-01), Havemann
patent: 4886764 (1989-12-01), Miller et al.

Affiliated with

Also associated with

Rating

Local interconnect process for integrated circuits does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Local interconnect process for integrated circuits, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Local interconnect process for integrated circuits will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-1365496