Glitch-proof powered-down on chip receiver with non-overlapping

Details Glitch-proof powered-down on chip receiver with non-overlapping Glitch-proof powered-down on chip receiver with non-overlapping

1991-04-10

1992-09-08

Miller, Stanley D.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

3072723, 307585, 307443, 36518806, 36518911, 36518905, H03K 513

Patent

active

051461110

ABSTRACT:
A circuit for providing a glitch-proof, powered-down inactive state to a memory array is disclosed. Cross-coupled NAND gates provide non-overlapping true/complement outputs for an on-chip receiver. Stable inactivation of both true and complement outputs is ensured without performance degrading delay stages.

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