Nonvolatile memory cell and method of producing the same

Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode

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257317, H01L 29788

Patent

active

054931401

ABSTRACT:
The nonvolatile memory cell of this invention includes a floating gate formed of an ultra-thin polycrystalline silicon film. Since the memory cell includes such an ultra-thin floating gate with a smooth surface, problems occurring in the patterning for the floating gate in conventional memory cells can be solved. In addition, the memory cells of the invention are suitable for device integration. Especially when the floating gate is formed of a polycrystalline silicon film, the device characteristics such as writing speed are remarkably improved.

REFERENCES:
patent: 5029130 (1991-07-01), Yeh
patent: 5045488 (1991-09-01), Yeh
patent: 5067108 (1991-11-01), Jeng
Salsbury et al, "High Performance MOS EPROMs Using a Stacked-Gate Cell", 1977 IEEE International Solid-State Circuits Conference.
Perlegos et al, "A 64K EPROM Using Scaled MOS Technology", 1980 IEEE International Solid-State Circuits Conference.
Buskirk et al, "A 200 ns 256K HMOSII EPROM", 1983 IEEE International Solid-State Circuits Conference.
Gupta et al, "A 5V-Only 16K EEPROM Utilizing Oxynitride Dielectrics and EPROM Redundancy", 1982 IEEE International Solid-State Circuits Conference.
Kynett et al, "An In-System Reprogrammable 256K CMOS Flash Memory", 1988 IEEE International Solid-State Circuits Conference.
Tam et al, "A High Density CMOS I-T Electrically Erasable Non-Volatile (Flash) Memory Technology", 1988 Symposium On VLSI Technology.
Woo et al, "A poly-Buffered FACE Technology for High Density Flash Memories", 1991 Symposium On VLSI Technology.
Sato et al, "An Ultra-Thin Fully Depleted Floating Gate Technology for 64 Mb Flash and Beyond", 1994 Symposium On VLSI Technology.

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