Static information storage and retrieval – Read/write circuit – Testing
Patent
1991-12-31
1993-10-19
LaRoche, Eugene R.
Static information storage and retrieval
Read/write circuit
Testing
365190, 365203, 371 211, G11C 2900
Patent
active
052552306
ABSTRACT:
The method of testing a memory array of SRAM cells each of which includes memory transistors, bit and bit# lines, precharge circuitry, and an output test terminal involving the steps of connecting selected bit and bit# lines of selected SRAM cells to the output test terminal, disconnecting the memory transistors of the selected SRAM cells from the bit and bit# lines, disconnecting the bit and bit# lines from the precharge circuitry, enabling the column select circuitry to select the columns of the selected SRAM cells, applying a preselected level voltage to the output test terminal, and measuring any current which flows.
REFERENCES:
patent: 4956819 (1990-09-01), Hoffmann et al.
patent: 4958324 (1990-09-01), Devin
patent: 4999813 (1991-03-01), Ohtsuka et al.
Chan James
Eskildsen Steve
Larsen Robert E.
Dinh Son
Intel Corporation
LaRoche Eugene R.
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