Static information storage and retrieval – Read/write circuit – Data refresh
Patent
1991-11-27
1993-05-11
LaRoche, Eugene R.
Static information storage and retrieval
Read/write circuit
Data refresh
36523003, G11C 800
Patent
active
052107175
ABSTRACT:
A dynamic random access memory device is periodically subjected to a refresh cycle for maintaining data bits stored in a plurality of memory cell arrays associated with a plurality of word line groups respectively coupled with a plurality of row address decoding units, and a refresh address counter increments a refresh address indicated by a refresh address signal for sequentially designating all the word lines of the word lines groups, wherein low-order address bits of the refresh address signal are supplied to a predecoding unit for sequentially allowing the row address decoding unit to respond to high-order address bits of the refresh address signal so that a refreshing operation of a component word line is carried out after recovery from undesirable voltage fluctuation occurred in the refreshing operation for the previous word line in the same word line group.
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patent: 3859640 (1975-01-01), Eberlem et al.
patent: 4758993 (1988-07-01), Takerae
patent: 4943947 (1990-07-01), Kobayashi
patent: 4972376 (1990-11-01), Torimaru et al.
patent: 5150329 (1992-09-01), Hoshi
LaRoche Eugene R.
NEC Corporation
Yoo Do Hyum
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