Semiconductor integrated circuit device employing MOSFETS

Details Semiconductor integrated circuit device employing MOSFETS Semiconductor integrated circuit device employing MOSFETS

1992-07-13

1993-10-19

Prenty, Mark V.

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

257369, H01L 2910, H01L 2702

Patent

active

052548651

ABSTRACT:
A MOSFET having a drain region consisting of a low concentration impurity diffused layer and a high concentration impurity diffused layer with shallow junction is employed. The variations of the device characteristics are averaged out and the life of the device as a whole is prolonged by increasing the length of the low concentration impurity diffused layer of an N-channel MOSFET, of a circuit whose operating conditions are susceptible to the hot electron effect as in the case of a CMOS address inverter which receives an address signal supplied as a TTL output, and by lowering the drain voltage by an advantageous use of the potential drop due to the resistance of the low concentration impurity diffused layer. The length of the low concentration impurity diffused layer of other MOSFETs is designed by considering the withstand voltage against punch-through between the drain and the source. In this way, it becomes possible to reduce the channel length compared with the case of a device with LDD structure.

REFERENCES:
patent: 4918501 (1990-04-01), Komori et al.
patent: 4937645 (1990-06-01), Ootsuka et al.
Patent Abstracts of Japan, vol. 13, No. 298 (E-784) Mar. 22, 1989.

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