MOS device having a well layer for controlling threshold voltage

Details MOS device having a well layer for controlling threshold voltage MOS device having a well layer for controlling threshold voltage

1992-08-10

1993-05-11

James, Andrew J.

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

257327, 257402, 257403, H01L 2978

Patent

active

052104370

ABSTRACT:
The present invention provides a semiconductor device having a well, formed in a semiconductor substrate by using a mask in which a mask pattern width of a portion corresponding to an opening diameter is equal to or less than twice the diffusion depth of the well layer, and a gate electrode formed to have the well layer as a channel region of a MOS transistor. The well formed in this manner has a substantially semi-circular section to facilitate impurity concentration control in the substrate surface. When a plurality of types of opening patterns having small pattern widths are formed in a single mask, MOS transistors having different threshold voltages can be formed in a single process.

REFERENCES:
patent: 4893164 (1990-01-01), Shirato
patent: 4987465 (1991-01-01), Longcor et al.
Patent Abstracts of Japan, vol. 11, No. 174 (E-513) (2621), Jun. 4, 1987; & JP-A-628553 (Toshiba) 16.01.1987.
Stengl et al., I.E.E.E. Transactions on Electron Devices, vol. ED-33, No. 3 Mar. 1986, pp. 426-428.

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