Semiconductor device having an interposing layer between an elec

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357 231, 357 233, 357 43, 357 65, H01L 2978, H01L 2701, H01L 2910, H01L 2702

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050328808

ABSTRACT:
In a semiconductor device, such as an IGBT and DMOS FET, a parasitic transistor is created between a first region (drift region) and third electrode region (emitter region) of the same conductivity type on one hand and the surface portion of a second electrode region (base region) of conductivity type opposite to that of the first-mentioned conductivity type on the other hand. An interposing layer formed of, for example, an opposite conductivity type poly-Si layer is formed in a manner to partially cover the emitter region and base region. A metal electrode film is formed as a connection electrode on the whole surface of a resultant structure such that it is in ohmic contact with the base region. The interposing layer is formed of a conductive layer and interposed with the metal electrode film formed not in direct contact with the third electrode region. The interposing layer is electrically so connected as to have some extent of resistance.

REFERENCES:
patent: 4502069 (1985-02-01), Schuh
patent: 4630084 (1986-12-01), Tihanyi
patent: 4878105 (1989-10-01), Hirakawa et al.
patent: 4903106 (1990-02-01), Fukunaga et al.
Patent Abstracts of Japan, vol. 10, No. 251 (E-432) (2307), Aug. 28, 1986, No. 61-80858, dated Apr. 24, 1986, Hitachi Ltd.
"Modern Power Devices", B. J. Baliga, pp. 369-370, 362.

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