Secondary cache write-through blocking mechanism

Details Secondary cache write-through blocking mechanism Secondary cache write-through blocking mechanism

1997-05-06

2000-07-25

Chan, Eddie P.

Electrical computers and digital processing systems: memory

Storage accessing and control

Hierarchical memories

711206, 711122, G06F 1300, G06F 1200

Patent

active

06094708&

ABSTRACT:
A cache blocking mechanism ensures that transient data is not stored in a secondary cache of a router by managing a designated set of buffers in a main memory of the router. The mechanism defines a window of virtual addresses that map to predetermined physical memory addresses associated with the set of buffers; in the illustrative embodiment, only transient data may be stored in these buffers. The mechanism further blocks write requests directed to these predetermined memory buffers from propagating to the secondary cache, thereby precluding storage of transient data in the cache.

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