Methods of identifying defects in an array of memory cells and r

Details Methods of identifying defects in an array of memory cells and r Methods of identifying defects in an array of memory cells and r

1999-07-01

2000-07-25

Nelms, David

Static information storage and retrieval

Read/write circuit

Testing

365190, G11C 700

Patent

active

060943882

ABSTRACT:
Methods of identifying defects in an array of memory cells and related integrated circuitry are described. In one embodiment, an array of memory cells is provided having a plurality of complementary digit line pairs. The digit line pairs comprise individual digit lines D0.sub.n, D0.sub.n.sup..cndot., where n>1. The complementary digit line pairs are configured to be placed into different states during sensing operations of the array. A defect-identifying signal is applied to the array by driving both digit lines of at least one digit line pair to a common test state, and the cell plate to another different test state with the use of only one dedicated bus line. In another embodiment, a pair of memory cells is provided each having an access transistor and a capacitor. The capacitor has a cell plate. Write circuitry is operably coupled with the pair of memory cells through respective individual input lines. The write circuitry is configured to write data into the memory cells. A defect-identifying condition is imposed on the array by placing the cell plate into a first test state, and, using the write circuitry, placing both of the input lines into a common second test state which is different from the first test state.

REFERENCES:
patent: 5848018 (1998-12-01), McClure

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