Semiconductor memory device with redundancy circuit

Details Semiconductor memory device with redundancy circuit Semiconductor memory device with redundancy circuit

1998-08-18

2000-07-25

Phan, Trong

Static information storage and retrieval

Read/write circuit

Bad bit

365201, G11C 700

Patent

active

060943815

ABSTRACT:
A semiconductor memory device is provided which is capable of realizing a redundancy memory cell test to be performed before a defective memory cell is replaced by a redundancy memory cell with a small size circuit provided therein. The semiconductor memory device includes a redundancy address program circuit programmed such that a redundancy memory cell is selected when an address for selecting a defective memory cell, for generating a redundancy selection signal, and a circuit for receiving a redundancy circuit test mode signal which is made active when the redundancy memory cell is tested before the redundancy address program circuit is programmed to generate a portion of the input address as a portion of the address of the redundancy memory cell when the redundancy circuit test mode signal is active and generate the redundancy selection signal as a portion of the address of the redundancy memory cell when the redundancy circuit test mode signal is inactive.

REFERENCES:
patent: 4942556 (1990-07-01), Sasaki et al.
patent: 5247481 (1993-09-01), Conan
patent: 5801986 (1998-09-01), Matsumoto et al.
patent: 5841709 (1998-11-01), McClure

Affiliated with

Also associated with

Rating

Semiconductor memory device with redundancy circuit does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Semiconductor memory device with redundancy circuit, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Semiconductor memory device with redundancy circuit will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-1341263