Output buffer circuit

Electronic digital logic circuitry – Interface – Supply voltage level shifting

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Details

326 68, 326 58, H03K 190175

Patent

active

060940670

ABSTRACT:
An output buffer circuit is provided which comprises a level conversion circuit having a first conversion circuit for converting a control signal and an output signal to "H" and "L" signals in a first source system and a second conversion circuit for converting these into "H" and "L" signals in a second source system, a tristate control type input/output control circuit for computing the "H" and "L" signals outputted from the second conversion circuit in the second source system, and a push-pull circuit having MOS transistors Q13a and Q14, which is activated in the second source system in response to the "H" and "L" signals so as to select a tristate and output it as an input/output signal.

REFERENCES:
patent: 4506164 (1985-03-01), Higuchi
patent: 5300835 (1994-04-01), Assar et al.
patent: 5422592 (1995-06-01), Asahina
patent: 5534795 (1996-07-01), Wert et al.
patent: 5670894 (1997-09-01), Takaishi et al.
patent: 5748011 (1998-05-01), Takaishi et al.
patent: 5834948 (1998-11-01), Yoshizaki et al.

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