Semiconductor memory device for shortening the set up time and h

Details Semiconductor memory device for shortening the set up time and h Semiconductor memory device for shortening the set up time and h

1996-11-22

1999-11-16

Zarabian, A.

Static information storage and retrieval

Read/write circuit

Simultaneous operations

365233, 365194, G11C 1604

Patent

active

059869437

ABSTRACT:
Shortening setup and hold times by equalizing the signal propagation delay time between input buffer circuits and D-F/F circuit to which are supplied command control signals CSB, RASB, CASB, and WEB supplied from a plurality of external terminals, and synchronizing these command control signals with the internal clock signal ICLK, batch loading these into D-F/F circuit and holding this signal, sending it from decode circuits after decoding, and latching it with latch circuits by means of internal clock delay signal ICLKD generated and delayed by internal clock signal ICLK thus being capable of shortening setup time and hold time in a synchronous DRAM.

REFERENCES:
patent: 5544124 (1996-08-01), Lagar
patent: 5581512 (1996-12-01), Kitamura
patent: 5600606 (1997-02-01), Rao
patent: 5631866 (1997-05-01), Oka
patent: 5694371 (1997-12-01), Kawaguchi

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