Electrical computers and digital processing systems: memory – Storage accessing and control – Specific memory composition
Patent
1996-02-09
1999-07-20
Chan, Eddie P.
Electrical computers and digital processing systems: memory
Storage accessing and control
Specific memory composition
711105, 711167, 365233, 36518901, 395551, 395881, G11C 700, G11C 1124
Patent
active
059268280
ABSTRACT:
A synchronous DRAM-type memory control is provided that allows continued and accurate data transfer to and from a synchronous DRAM (syncDRAM) memory for special cases where data is not ready to be transferred. In the event that data is not ready to be transferred between a destination device and the syncDRAM, transfer of data is suspended. Concurrently, at the address from which data was not ready to be transferred, the address is latched by a syncDRAM interface that communicates with the system memory control and the syncDRAM memory. In the event of a read cycle, back to back read requests are asserted until data can be transferred. In the event of a write request, a mask command is asserted to mask out the data address in the syncDRAM until data is ready to be written to the address, wherein the write request is then reasserted. For both read and write cycles, when data is subsequently ready to be transferred, data transfer is resumed at the latched address. This effectively replaces the clock enable functionality and provides cost savings and die size savings.
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Chan Eddie P.
Intel Corporation
Kim Hong C.
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