Test structure for determining how lithographic patterning of a

Active solid-state devices (e.g. – transistors – solid-state diode – Test or calibration structure

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324765, 324769, 438 11, 438 18, H01L 2358, G01R 3126

Patent

active

059862831

ABSTRACT:
The present invention advantageously provides a test structure and method for determining how lithographic patterning of transistor gate conductors laterally spaced from conductors affects the operation of transistors which employ the gate conductors. The test structure includes a sequence of gate conductors interposed above and between a respective sequence of source and drain regions. The test structure further includes a sequence of conductors which have been patterned from the same material as the gate conductors. The conductors are spaced an increasing distance from respective gate conductors. The gate conductors extend beyond the respective source and drain regions by varying distances or by the same distance. Lithographic patterning of the gate conductors and the conductors may result in the edges of the gate conductors and the conductors being substantially round and absent of sharp corners. Further, lithographic patterning may lead to a reduction in the lengths of the gate conductors and the conductors. The length of each gate conductor extends along the same axis as the length of the conductor nearest to the gate conductor.

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patent: 5707765 (1998-01-01), Chen
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patent: 5773315 (1998-06-01), Jarvis

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