Fuse option for multiple logic families on the same die

Details Fuse option for multiple logic families on the same die Fuse option for multiple logic families on the same die

1997-08-14

1999-07-20

Santamauro, Jon

Electronic digital logic circuitry

Multifunctional or programmable

326 82, 327525, H03K 19173

Patent

active

059260343

ABSTRACT:
A chip's interface is selected by using a fuse option coupled between integrated circuitry on the chip and logic circuitry. Fuse options correspond to antifuses or fuses. In one embodiment, a plurality of fuse options are manufactured in an integrated circuit such that a fuse option is coupled between integrated circuitry on the chip and separate and complete logic circuitry for different logic types used to interface a chip. In another embodiment, only one type of logic circuitry is manufactured on a chip, such that the logic circuitry has both a pull-up and pull-down transistor. A fuse is coupled with a pull-up control circuit of the logic circuitry. When the fuse is blown, the output circuit corresponds to GTL-terminated logic circuitry, using only the pull-down transistor. In a further embodiment, an antifuse is coupled with the pull-up control circuit. When the antifuse is programmed, default GTL-terminated logic is converted to TTL family output logic, or another logic which uses both pull-up and pull-down transistors in its logic circuitry.

REFERENCES:
patent: 4223277 (1980-09-01), Taylor et al.
patent: 4959564 (1990-09-01), Steele
patent: 5099148 (1992-03-01), McClure et al.
patent: 5107230 (1992-04-01), King
patent: 5128560 (1992-07-01), Chern et al.
patent: 5257225 (1993-10-01), Lee
patent: 5281868 (1994-01-01), Morgan
patent: 5282158 (1994-01-01), Lee
patent: 5324681 (1994-06-01), Lowrey et al.
patent: 5331196 (1994-07-01), Lowrey et al.
patent: 5345110 (1994-09-01), Renfro
patent: 5361003 (1994-11-01), Roberts
patent: 5373199 (1994-12-01), Shichinohe et al.
patent: 5379250 (1995-01-01), Harshfield
patent: 5514980 (1996-05-01), Pilling et al.
patent: 5526317 (1996-06-01), McClure
patent: 5566107 (1996-10-01), Gilliam
patent: 5703496 (1997-12-01), Sabin
patent: 5712588 (1998-01-01), Choi et al.
patent: 5726585 (1998-03-01), Kim
patent: 5748031 (1998-05-01), Bets
patent: 5821783 (1998-10-01), Torimaru et al.
"Interface Standard for Nominal 3V/3.3V Supply Digital Integrated Circuits", JEDEC Standard, Electronic Industries Association, 1-4, (Jun. 1994).

Affiliated with

Also associated with

Rating

Fuse option for multiple logic families on the same die does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Fuse option for multiple logic families on the same die, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Fuse option for multiple logic families on the same die will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-1324799