Asymmetric S/D structure to improve transistor performance by re

Details Asymmetric S/D structure to improve transistor performance by re Asymmetric S/D structure to improve transistor performance by re

1997-10-06

1999-07-20

Prenty, Mark V.

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

438163, 438286, H01L 2976

Patent

active

059259140

ABSTRACT:
A method of making a transistor is also disclosed, including the steps of forming a gate oxide layer (106) over a semiconductor substrate (100) and forming a gate structure (108) over a portion of the gate oxide layer (106), thereby separating the transistor into a first region (114) and a second region (112) with a channel region therebetween. The method also includes forming a source region (114) having a source LDD portion (116) and forming a drain region (112) having a drain LDD portion (124) in the second region (112), wherein the drain LDD portion (124) is more shallow than the source LDD portion (1 16). An asymmetric source/drain LDD transistor structure includes a semiconductor substrate (100), a gate oxide layer (106) overlying the substrate (100) and a gate structure (108) overlying the gate oxide layer (106). The transistor structure further includes a source region (129) and a drain region (128) formed in the semiconductor substrate (100) on opposite sides of the gate structure (108) which forms a channel region therebetween. A drain LDD region (124) is disposed between the drain region (128) and the channel and a source LDD region (116) is disposed between the source region (129) and the channel, wherein the drain LDD region (124) is more shallow than the source LDD region (116).

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IEEE Transactions on Electron Devices, vol. 41, No. 2., Feb. 1994, pp. 186-190, "An Asymmetric Sidewall Process for High Performance LDD MOSFET's" by Tadahiko Horiuchi, Tetsuya Homma, Yuikinobu Murao and Koichior Okumura.
International Electron Devices Meeting Technical Digest (IEDM), Jul. 1989, pp. 617-620, "Asymmetrical Halo Source GOLD Drain (HS-GOLD) Deep Sub-Half Micron n-MOSFET Design for Reliability and Performance" by T. N. Buti, S. Ogura, N. Rovedo, K. Tobimatsu, C.F. Codella.

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