Electrically programmable read-only memory array

Details Electrically programmable read-only memory array Electrically programmable read-only memory array

1995-04-17

1996-09-10

Limanek, Robert P.

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

257326, 257900, H01L 29788

Patent

active

055548695

ABSTRACT:
Flash EEPROM cells having merged select/control gates may be formed, so that the portions of the channel regions that correspond to select transistors are formed after spacers are formed but prior to patterning a merged select/control gate layer. Because the portions of the channel regions that correspond to the select transistors are not determined by the patterning of the merged select/control gate layer, misalignment of the mask used to pattern the merged select/control gate layer does not affect the size of the select transistor portion of the channel region. The spacers may be left on over the substrate in the finished devices thereby saving at least one processing step. The memory structure may also be used in other EPROM-type memory cells, such as individually erasable EEPROMs and EPROMs that are not electrically erasable.

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Heinrich, et al.; "A 0.5 um CMOS Technology for Multifunctional Applications with Embedded FN-Flash Memory and Linear R and C Modules"; IEDM; pp. 445-448 (1993).
Yamauchi, et al.; "A Novel Source-Side Injection Split-Gate Flash Cell Technology for High Density Low Voltage Applications;" 1994 Int'l Conf. on Solid State Devices and Mat'ls (1994).

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