Crater prevention technique for semiconductor processing

Details Crater prevention technique for semiconductor processing Crater prevention technique for semiconductor processing

1994-07-19

1995-06-13

Hille, Rolf

Active solid-state devices (e.g., transistors, solid-state diode

Combined with electrical contact or lead

Configuration or pattern of bonds

257754, 257760, H01L 2348, H01L 2940

Patent

active

054245818

ABSTRACT:
A semiconductor bond pad prevents cratering by including an etch stop layer which is formed between the field oxide layer and the first dielectric layer to prevent erosion of the field oxide while allowing etching and removal of the first dielectric layer to prevent cratering.

REFERENCES:
patent: 4810666 (1989-03-01), Taji
patent: 4916084 (1990-04-01), Shibata
patent: 5084752 (1992-01-01), Satoh et al.
patent: 5094980 (1992-03-01), Shepela
Bond Pad Structure Reliability, Ching et al., IEEE/IRPS 1988, pp. 64-70.
VLSI Fabrication Principles, S. Ghandhi, Rensselaer Polytechnic Institute pp. 432-435.
A Bond Failure Mechanism, Koch et al., IEEE/IRPS 1986, pp. 55-60.

Affiliated with

Also associated with

Rating

Crater prevention technique for semiconductor processing does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Crater prevention technique for semiconductor processing, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Crater prevention technique for semiconductor processing will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-1311565