Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Patent
1992-11-10
1995-06-13
Loke, Steven Ho Yin
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
257382, 257412, 257588, 257755, H01L 2976, H01L 2994, H01L 2348
Patent
active
054245729
ABSTRACT:
A contact structure and a method for fabrication is disclosed for a semiconductor device that includes a plurality of semiconductor regions along the surface of the device, each region having a top surface and at least a sidewall surface, where a first part of the semiconductor regions are of a first conductivity type and a second part of semiconductor regions are of a second conductivity type. Select dielectric spacers are formed along the sidewalls of the select semiconductor regions of first conductivity type while a refractory metal such as titanium, molybdenum or tungsten is used to form contact on the sidewalls of the semiconductor regions of second conductivity type. This structure is most advantageous in bipolar, CMOS and BiCMOS transistor structures as it allows the formation of the sidewall spacers on emitter/gate contacts while having local metal interconnects with the reactive metal on the sidewall of the select base/source/drain contacts.
REFERENCES:
patent: 3955269 (1976-05-01), Magdo et al.
patent: 4484388 (1984-11-01), Iwasaki
patent: 4507847 (1985-04-01), Sullivan
patent: 4536945 (1985-08-01), Gray et al.
patent: 4609568 (1986-09-01), Koh et al.
patent: 4764480 (1988-08-01), Vora
patent: 4927775 (1990-05-01), Alvarez et al.
patent: 4927776 (1990-05-01), Soejima
patent: 4960726 (1990-10-01), Lechaton et al.
patent: 4965220 (1990-10-01), Iwasaki
patent: 4979010 (1990-12-01), Brighton
patent: 5001081 (1991-03-01), Tuntasood et al.
patent: 5021354 (1991-06-01), Pfiester
patent: 5045483 (1991-09-01), DeLong et al.
E. A. Irene, "Silicon Oxidation Sutdies: The Oxidation of Heavity B- and P-Doped Single Crystal Silicon," J. Electrochem. Soc.: Solid-State Science and Tech., Jul. 1978, pp. 1146-1151.
H. H. Berger et al. "Method of Producing Transistors with Optimum Base Contact," IBM Technical Disc. Bulletin, vol. 23, No. 4, Sep. 1980.
Sorab K. Ghandhi, VLSI Fabrication Principles, Silicon and Gallium Arsenide, John Wiley & Sons, 1983, pp. 383-384, 493-494.
H. Momose et al. "1.0 .mu.m n-Well CMOS/Bipolar Technology," IEEE Trans. on Electron Devices, vol. ED-32, No. 2, Feb. 1985.
A. K. Kapoor et al. "A High-Speed, High-Density Single-Poly ECL Technology for Linear/Digital Applications," IEEE Custom Integrated Circuits Conference, pp. 184-187, 1985.
T. Gomi et al. "A Sub-30 psec Si Bipolar LSI Technology," IDEM, pp. 744-746, IEEE, 1988.
M. P. Brassington, et al. "An Advanced Single-Level Polysilicon Submicrometer BiCMOS Tech.," IEEE Trans. on Electron Devices, vol. 36, No. 4, Apr. 1989.
Loke Steven Ho Yin
National Semiconductor Corporation
LandOfFree
Spacer formation in a semiconductor structure does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Spacer formation in a semiconductor structure, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Spacer formation in a semiconductor structure will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-1311455