Semiconductor memory device

Static information storage and retrieval – Powering

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Details

36518907, 36518909, 36518911, 327536, G11C 700

Patent

active

058055193

ABSTRACT:
A semiconductor memory device includes a memory cell array and a low potential setting circuit. An n channel transistor of one example of the low potential setting circuit receives a signal .phi. from an operation signal control circuit at its gate before operation of an internal circuit to be turned on, thereby decreasing the potential of a BSG line to a level which is close to ground potential. As a result, the increase in the potential level of the BSG line based on inflow of positive electric charge caused by operation of the internal circuit can be prevented, and the potential differences between the source and the drain and between the source and the gate of the n channel transistor can be increased. As a result, the operation speed of the internal circuit can be increased. More specifically, the access time of the semiconductor memory device is shortened.

REFERENCES:
patent: 5258950 (1993-11-01), Murashima et al.
patent: 5295112 (1994-03-01), Taniguchi
patent: 5327388 (1994-07-01), Kobayashi

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