Semiconductor memory device with reduced leak current

Details Semiconductor memory device with reduced leak current Semiconductor memory device with reduced leak current

1997-01-08

1998-09-08

Yoo, Do Hyun

Static information storage and retrieval

Read/write circuit

Including reference or bias voltage generator

36518907, 365203, 365207, 365226, G11C 700

Patent

active

058055088

ABSTRACT:
In a data holding mode, a potential on a substrate region in a memory cell array is fixed at the same level as that in a normal operation mode, and an absolute value of a bias voltage applied to a substrate region in a peripheral circuit is made larger than that in the normal operation mode. When an operation mode changes, a memory cell transistor substrate potential does not change, and therefore a potential on a storage node of a memory cell does not change, so that the storage data is stably held. A threshold voltage of an MOS transistor in the peripheral circuit increases in absolute value, and a subthreshold current is reduced. A current consumption is reduced in the data holding mode of a semiconductor memory device without adversely affecting storage data.

REFERENCES:
patent: 5404335 (1995-04-01), Tobita
patent: 5568440 (1996-10-01), Tsukude et al.
patent: 5604707 (1997-02-01), Kuge et al.
patent: 5677889 (1997-10-01), Haraguchi et al.
"Standby power consumption is reduced to a conventional level by . . . ", Kuroda et al., Nikkei Microdevices Mar. 1995, pp. 58-60.

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