Method for forming a cylindrical capacitor

Details Method for forming a cylindrical capacitor Method for forming a cylindrical capacitor

1997-06-18

1998-04-07

Nguyen, Tuan H.

Semiconductor device manufacturing: process

Making passive device

Stacked capacitor

438397, 438253, 438254, 438738, 148DIG14, H01L 2120

Patent

active

057364508

ABSTRACT:
An improved process for fabricating cylindrical capacitors for use in DRAMs is described wherein the silicon nitride etch stop layer is eliminated. The etch stop layer is normally used to halt etching during the formation of the dielectric cylinder that is used as a substrate on which the cylindrical electrode gets built. If etching is allowed to proceed, the underlying dielectric layer on which the cylinder rests will also be removed. In place of the etch stop layer, the present invention calls for two dielectric layers that have generally similar properties in other respects but substantially different etch rates. For the fast etching dielectric, O.sub.3 TEOS is used while, for the slow etching dielectric, BPTEOS is used. When etched in 10:1 BOE a differential etch rate of about 10 times is obtained so that formation of a O.sub.3 TEOS cylindrical substrate can be completed without significantly eroding the underlying BPTEOS support layer.

REFERENCES:
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patent: 5436187 (1995-07-01), Tanigawa
patent: 5506164 (1996-04-01), Kinoshita et al.
patent: 5543346 (1996-08-01), Keum et al.
patent: 5550076 (1996-08-01), Chen
patent: 5663092 (1997-09-01), Lee
patent: 5668038 (1997-09-01), Huang et al.

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