Semiconductor memory device with redundancy circuit

Details Semiconductor memory device with redundancy circuit Semiconductor memory device with redundancy circuit

1988-07-28

1989-08-15

Moffitt, James W.

Static information storage and retrieval

Read/write circuit

Bad bit

G11C 700

Patent

active

048581925

ABSTRACT:
A semiconductor memory device has a redundancy circuit for compensating a defective bit when it occurs in the main memory cells. The redundancy circuit includes spare memory cells, a spare row decoder for selecting the spare memory cells, a first circuit section for inhibiting the use of the main row decoder when the spare row decoder is used, and a second circuit section for selecting the spare row decoder when an address specifying the main row line connected to the defective memory cell is denoted.

REFERENCES:
patent: 4441170 (1984-04-01), Folmsbee et al.
patent: 4635232 (1987-01-01), Iwahashi et al.
patent: 4648075 (1987-03-01), Segawa et al.
patent: 4750158 (1988-06-01), Giebel et al.
patent: 4754434 (1988-06-01), Wang et al.

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