Method of making an underlayer to reduce pattern sensitivity of

Details Method of making an underlayer to reduce pattern sensitivity of Method of making an underlayer to reduce pattern sensitivity of

1997-08-06

1998-09-08

Bowers, Jr., Charles L.

Semiconductor device manufacturing: process

Coating with electrically or thermally conductive material

To form ohmic contact to semiconductive material

438763, 438789, H01L 214763

Patent

active

058044981

ABSTRACT:
An improved method of ozone-TEOS deposition with reduced pattern sensitivity and improved gap filling capability is described. Semiconductor device structures are provided in and on a semiconductor substrate. A conducting layer is deposited overlying the surfaces of the semiconductor device structures and patterned to form conducting lines wherein the conducting lines are dense in some portions of the semiconductor substrate and sparse in other portions of the substrate and wherein gaps are formed between the conducting lines. A nucleation layer is formed by depositing a first pattern sensitivity reducing layer over the surfaces of the conducting layer and then depositing a first oxide layer overlying the first dielectric layer. A second oxide layer is deposited over the nucleation layer wherein the gap is filled by the second oxide layer and the fabrication of integrated circuit is completed.

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Korczynski et al, "Improved Sub-Micron Inter-Metal Dielectric Gap-Filling Using TEOS/Ozone APCVD", Microelectronics Manufacturing Technology, Jan. 1992, pp. 22-27.

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