Method of fabricating a bottom and top gated thin film transisto

Details Method of fabricating a bottom and top gated thin film transisto Method of fabricating a bottom and top gated thin film transisto

1996-12-20

1998-04-07

Trinh, Michael

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

On insulating substrate or layer

438153, 438596, H01L 2100

Patent

active

057364370

ABSTRACT:
An electrical interconnection method includes: a) providing two conductive layers separated by an insulating material on a semiconductor wafer; b) etching the conductive layers and insulating material to define and outwardly expose a sidewall of each conductive layer; c) depositing an electrically conductive material over the etched conductive layers and their respective sidewalls; and d) anisotropically etching the conductive material to define an electrically conductive sidewall link electrically interconnecting the two conductive layers. Such is utilizable to make thin film transistors and other circuitry.

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Colinge, J., et. al., "Silicon-On-Insulator `Gate-All-Around Device`", IEEE, IEDM 90-595-99 (1990).
Tanaka, T., et. al., "Analysis of P.sup.+ PolySi Double-Gate Thin-Film SOI MOSFETS", IEEE, IEDM 91-683-86 (1991).

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