Semiconductor memory circuit with improved bit lane precharge ci

Details Semiconductor memory circuit with improved bit lane precharge ci Semiconductor memory circuit with improved bit lane precharge ci

1988-12-27

1990-07-24

Fears, Terrell W.

Static information storage and retrieval

Read/write circuit

Differential sensing

365203, 36518906, 365205, 365333, G11C 1300

Patent

active

049439529

ABSTRACT:
A dynamic memory circuit provided with an improved bit line reference voltage control circuit realized by a small capacitance of an adjustment capacitor is disclosed. The memory circuit includes a short-circuiting circuit for setting each pair of bit lines at an intermediate voltage of a power source voltage, a capacitor for lowering the intermediate voltage according to charge division based on a ration of a capacitance of the adjustment capacitor and a total capacitance of the bit lines, and a boot-strap circuit for operatively causing a level reduction more than the power source voltage in the capacitor.

REFERENCES:
patent: 4677313 (1987-01-01), Mimoto
patent: 4716313 (1987-12-01), Hori et al.
patent: 4794571 (1988-12-01), Uchida
patent: 4813022 (1989-03-01), Matsui et al.

Affiliated with

Also associated with

Rating

Semiconductor memory circuit with improved bit lane precharge ci does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Semiconductor memory circuit with improved bit lane precharge ci, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Semiconductor memory circuit with improved bit lane precharge ci will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-1271474