Serially accessible semiconductor memory with multiple level sto

Details Serially accessible semiconductor memory with multiple level sto Serially accessible semiconductor memory with multiple level sto

1991-11-27

1994-09-27

LaRoche, Eugene R.

Static information storage and retrieval

Read/write circuit

36518912, 365210, 365221, G11C 700, G11C 702

Patent

active

053512103

ABSTRACT:
According to this invention, in a data bit array for storing data, a plurality of memory cells capable of storing 4-level data are arranged in column and row directions. A check bit array for storing check data has a number of bits smaller than that of the data bit array. In the check bit array, a plurality of memory cells capable of storing 4-level data are arranged in column and row directions. A row address decoder selects one row from the check bit array and the data bit array in accordance with address data. Three sense amplifiers are connected to one column of the check bit array and the data bit array. The three sense amplifiers detect levels of data read from a memory cell in accordance with different reference levels in data read access, receive a plurality of precharge levels corresponding to 4-level write data, and write one of the precharged levels in the corresponding memory cell in accordance with write data. A data converter converts levels of data detected by the sense amplifiers into 2-bit data in data read access and selects a sense amplifier in accordance with write data having a plurality of bits in data write access. An input/output circuit serially outputs data supplied from the data converter in data read access and supplies external write data to the data converter in data write access.

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patent: 4819213 (1989-04-01), Yamaguchi et al.
patent: 4841483 (1989-06-01), Furuyama
patent: 4888630 (1989-12-01), Paterson
patent: 4890259 (1989-12-01), Simko
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patent: 5172339 (1992-12-01), Noguchi et al.
An Experimental 2-bit/Cell Storage DRAM for Macrocell or Memory-on-Logic Application, Tohru Furuyama et al., IEEE Journal of Solid State Circuits, vol. 24, No. 2, pp. 388-398, Apr. (1989).
A 16-Levels/Cell Dynamic Memory, Masakazu Aoki et al., IEEE International Solid-State Circuits Conference, pp. 246-247, Feb. 15, 1985.

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