Write-buffer FIFO architecture with random access snooping capab

Details Write-buffer FIFO architecture with random access snooping capab Write-buffer FIFO architecture with random access snooping capab

1998-01-16

2000-11-21

Robertson, David L.

Electrical computers and digital processing systems: memory

Storage accessing and control

Specific memory composition

711117, 711154, G06F 1300

Patent

active

061516589

ABSTRACT:
A system provides a write buffer with random access snooping capability. A random access write buffer includes a write buffer controller and a random access memory (RAM) containing a content addressable memory (CAM) address store and a random access memory data store. The CAM compares an input write address from a producer to the addresses present in the address store. If the input write address is "related" to an address present in the address store, the CAM detects an address hit. The indication of an address hit is provided to the write buffer controller which signals the data store to store the input write data in the existing rank of the data store associated with the "related" address detected by the CAM. The CAM also detects whether an input read address provided by a producer to a consumer is "related" to an address in the address store. If the input read address is "related" to an address in the address store, the read data at the "related" address in the address store is retrieved and merged with the read data from the consumer to produce valid read data. The valid read data is then provided to the producer. The write buffer thus enhances a general FIFO function with write merging, write collapsing, and read merging.

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