Computer system deadlock request resolution using timed pulses

Details Computer system deadlock request resolution using timed pulses Computer system deadlock request resolution using timed pulses

1998-04-30

2000-11-21

Auve, Glenn A.

Electrical computers and digital data processing systems: input/

Access arbitrating

Access prioritizing

710 40, 711151, G06F 1200

Patent

active

061516554

ABSTRACT:
Disclosed is a hardware mechanism for detecting and avoiding potential deadlocks among requestors in a multiprocessor system, consisting of a plurality of CP's and I/O adapters connected to one or more shared storage controllers (SC's). Requests to each storage controller originate from external sources such as the CP's, the I/O adapters, and the other SC, as well as from internal sources, such as the hardware facilities used to process fetches and stores between the SC and main memory. All requests must be granted priority before beginning to execute, using a ranked priority order scheme. Specific sequences of requests may cause deadlocks, either due to high-priority requests using priority cycles and locking out low-priority requests, or as a result of requests of any priority level busying resources needed for the completion of other requests. The deadlock resolution mechanism described here monitors the length of time a request has been valid in the storage controller without completing, by checking the request register valid bits and utilizing a timed pulse, which is a subset of the pulse used to detect hangs within the SC. If the valid bit for a request register is on, and two timed pulses are received, an internal hang detect latch is set. If the valid bit is reset at any time, the detection logic and the internal hang detect latch are reset. When the internal hang detect latch is set, requests in progress are allowed to complete, and new requests are held in an inactive state, until the request which detected the internal hang is able to complete.

REFERENCES:
patent: 4937733 (1990-06-01), Gillett, Jr. et al.
patent: 5016167 (1991-05-01), Nguyen et al.
patent: 5025370 (1991-06-01), Koegel et al.
"Precise Method to Prevent Lockout in an Input/Output Priority Queueing System" IBM Technical Disclosure Bulletin, vol. 39, No. 12, Dec. 1996, pp. 117-118.
"Low Cost Multiple Hang Timers" IBM Technical Disclosure Bulletin, vol. 31, No. 8, Jan. 1989.
"Detection of Element/System Timeouts" IBM Technical Disclosure Bulletin, Jul. 1990, No. 315.
"Prevention of Low Priority Lockout" IBM Technical Dislosure Bulletin, Feb. 1987, No. 274.

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