Static information storage and retrieval – Floating gate – Particular biasing
Patent
1999-12-21
2000-11-21
Le, Vu A.
Static information storage and retrieval
Floating gate
Particular biasing
36518517, 36518529, G11C 1604
Patent
active
061512524
ABSTRACT:
In a flash memory EEPROM, a memory cell MC is formed in a P-type semiconductor substrate. A peripheral transistor TR is formed in an N-type well. Another peripheral transistor TR is formed in a P-type well. The P-type well is by turn formed an N-type well and electrically insulated from the substrate. The substrate is typically provided with a metal back structure and its substrate voltage is set to predetermined voltages respectively for data erasure, data storage and data retrieval. With such an arrangement, the level of voltage stress with which the device is loaded during data erasure can be remarkably reduced to allow a down-sizing and an enhanced quality to be realized for the device.
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Atsumi Shigeru
Tanaka Sumio
Kabushiki Kaisha Toshiba
Le Vu A.
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