Method for making polycide-to-polycide low contact resistance co

Details Method for making polycide-to-polycide low contact resistance co Method for making polycide-to-polycide low contact resistance co

1996-03-19

2000-11-21

Quach, T. N.

Semiconductor device manufacturing: process

Coating with electrically or thermally conductive material

Insulated gate formation

438647, 438649, 438655, H01L 213205

Patent

active

061502472

ABSTRACT:
A method for making interlevel contacts having low contact resistance (R.sub.c) between patterned polycide layers is described. The method and resulting contact structure consists of depositing and conductively doping a first polysilicon layer having a first tungsten silicide (WSi.sub.2) layer. The first polysilicon/silicide (first polycide) layer is patterned to form the first polycide interconnecting conducting layer. An insulating layer is deposited over the patterned first polycide layer and contact openings are anisotropically plasma etched in the insulating layer to the underlying polycide layer. The etching is continued to remove completely the first silicide layer in the contact openings, and to etch into the first polysilicon layer. After a brief hydrofluoric (HF) etch, a second doped polysilicon layer is deposited and patterned to form a second conducting interconnecting level over the contact openings. The second polysilicon-to-first polysilicon interface formed in the contacts results in consistently low contact resistance (R.sub.c). This low R.sub.c is difficult to achieve in the prior art where the second level metallurgy contacts the first tungsten silicide of the first level interconnecting polycide layer.

REFERENCES:
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patent: 5395784 (1995-03-01), Lu et al.
patent: 5468669 (1995-11-01), Lee et al.
Wolf, S., et al., Silicon Processing, vol. 1, 1986, Lattice Press, pp. 181-182, 384-386, 581.

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