Register-read acknowledgment and prioritization for integration

Details Register-read acknowledgment and prioritization for integration Register-read acknowledgment and prioritization for integration

1993-01-04

1996-10-15

Lee, Thomas C.

Boots, shoes, and leggings

39520006, 39520016, 395478, 395733, 3642301, 3642302, 3642808, 3642632, 3642412, G06F 900, G06F 946

Patent

active

055663524

ABSTRACT:
A register-based computer architecture is particularly suited for using a common resource, such as a host processor or CPU, to respond to multiple devices such as co-processors, slave processors, or peripherals via service requests initiated by these devices. The invention's register acknowledgment and service prioritizing features are preferably added to, and integrated with, a prior-art, hardware-based interrupt acknowledgment mechanism, thus providing enhanced flexibility and performance. This architecture includes features for enhancing the support of a service-request based or queue-driven interface between the host processor and the supported devices, including a Service Request Status Register, a Service Request Configuration Register, and Service Request Acknowledge Register(s). From the point of view of the host processor, these registers are accessed as normal input/output read/write operations. From the point of view of the supported devices, such register operations appear to be interrupt acknowledgment operations. This transformation is effected by special-purpose logic within the architecture. The invention is preferably embodied in a monolithic integrated circuit that supports control by the host processor of a potentially large number of data communications ports. These features can be incorporated in pin compatible new versions of existing devices so as to be backwards compatible with the existing devices, thus allowing end users to gracefully upgrade their systems with minimal effort.

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CL-CD1400 Data Book, Cirrus Logic, Inc., Sep. 1993, pp. 1-131.

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