Read and write circuitry for a memory

Details Read and write circuitry for a memory Read and write circuitry for a memory

1992-07-10

1994-06-14

LaRoche, Eugene R.

Static information storage and retrieval

Read/write circuit

36518902, 36518907, 36518908, 36523002, 365 49, G11C 700

Patent

active

053216512

ABSTRACT:
A memory is provided with at least one temporary store and write abort circuitry having a control signal store and gating circuitry responsive to an output from the control signal store. Write circuitry loads data and an associated address in the temporary store during one write cycle and transfer circuitry transfers the data to the associated address during a subsequent write cycle when the write operation is not to be aborted. Read circuitry includes a comparator for comparing a read address with an address in the temporary store and transfer circuitry includes selection circuitry to select an output of data either from the temporary store or the memory dependent on the output of the comparator circuitry, an output from the temporary store being prevented if the control signal store indicates that the write operation is to be aborted.

REFERENCES:
patent: 4670858 (1987-06-01), Almy
patent: 4882709 (1989-11-01), Wyland
patent: 5148396 (1992-09-01), Nakada
patent: 5239642 (1993-08-01), Gutierrez et al.

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